8 Way DMux

In the last exercise, we implemented a 4 way DMux.

In this exercise, we will implement an 8 way DMux. For an 8 way DMux, we need 3 selector pins.

Here we can use one regular (2 way) DMux, and two 4 way DMux's we created in the previous exercise.

Till now, when cascading, I have started from selector[0] and then moved towards selector[n]. In this example I am going the opposite way. We will start with selector[2] and then move on to selector[1] and selector[0].

If you look at the truth table, selector 0 can be used to create 2 sets. The first set, when selector[0] is 0, can result in the output being routed to 'a', 'b', 'c', or 'd'. The second set, when selector[2] is 1, can result in the output being routed to 'e', 'f', 'g', or 'h'.

Here, since we are fanning out into 2 sets, we need to use a regular (2 way) DMux. This DMux will have 2 output lines. Each of these output lines will be fed into a 4 way DMux to create a total of 8 output lines.

The code for the exercise is embedded below.

4 Way DMux

In this exercise, we will build a 4 way DMux.

We have already implemented a simple (2 way) DMux. In that there is one input line, and one selector. The value of the selector, determines, which output line the input is routed to.

In a 4 way DMux, we have 1 input line, 4 possible output lines, and 2 selectors. Based on the value of the selector, the input line is router to one of the 4 output lines.

We can implement a 4 way DMux, using multiple regular (2 way) DMux's. If we look at the truth table, we will notice that if selector[0] is 0, then in can be routed to either 'a', or 'c' (based on the value of selector[1]). If selector[0] is 1, then the input can be sent to either 'b', or 'd' (based on the value of selector[1]).


The code for the 4 way DMux us specified below.

Mux 8 way, 16 bit

In this exercise, we build an 8 way, 16 bit Mux. What this means is that there are eight input arrays (of 16 bits each), for which we will need 3 selectors, and these selectors will select one of the eight input lines to appear as the output.

If we look at the truth table below, we notice that we can apply a 4 way Mux to lines A,B,C,D (using sel[0], ans sel[1]) and another 4 way Mux to E, F, G, H (using sel[0], ans sel[1]). This will result in two lines (one from each set moving ahead). We can then apply a simple Mux to select from one of them, using sel[2].

The code for the 8 way 16 bit Mux is embedded below:

Mux 4 way 16 bit

A 4 way, 16 bit Mux is a Mux which which can select among 4 input lines. To select from 4 input lines, we need log24 selectors.

Because this is a 16 bit Mux, each input line is an array of 16 bits.

Looking at the truth table for the Mux, we know that if sel[0] is 0, then line 'a', and 'c', can be selected. While if sel[0] is 1, then line 'b', or line 'd' are selected. So basically sel[0] will cause one set ('a','c' or 'b','d') to be selected.

sel[1], will select one line from the winner.

So, if sel[0] is 0, then the set 'a', 'c' is the winning set, from which one line will be selected by sel[1]. If sel[0] is 1, then set 'b', 'd' is the winning set from which one line will be selected by sel[1].

The code for the 4 way, 16 bit Mux is specified below.

Built an 8 way OR chip

In this activity, we have to build an 8 way OR chip. An 8 way chip is a specific case of an n-ary chip. It takes n (in this case 8) inputs.

An 8 way Or chip, basically takes 8 inputs and applies the OR function on all of them, and finally provides the output on it's 'out' line.

We will built an 8 way OR chip, using the regular 2 pin OR chip, which we have already built.

We have to cascade multiple of these chips to get the output. There are different ways to cascade them... some more efficient than others.

The code for this activity is embedded below.

Built a 16 bit Mux

Built a 16 bit Mux. A 16 bit Mux is very similar to a regular Mux, except that instead of receiving it's input from 2 pins, it receives it's input from an 2, 16 bit arrays. Code for the 16 bit Mux is embedded below.

Or 16 bit chip

The 16 bit Or chip is again very similar to the 16 bit And chip, except that we use the Or chip to connect the input lines with their corresponding output lines.

And 16 bit chip

The 16 bit And chip is similar to the 16 bit Not chip, except that we use the And chip to connect all the 16 input lines to their corresponding 16 output lines. The code is embedded below.

Not16 Chip

The Not16 chip is very similar to the Not chip, except that it has 16 input lines and corresponding 16 output lines.

We need to use 16 Not chips, where we connect each input line to the corresponding output line. I thought HDL might have a loop structure where I could specify the 6 Not chips, but looks like it does not. Had to manually specify the 16 Not chips. The code for the chip is specified below.

Building a DMux

A DMUX is the opposite of MUX. It recieves one input and based on the value of the selector bit, it routes that input to one of two output lines.

Looking at the image above, if sel is 0, then the value of 'in' will be routed to O0, and if sel is 1, then the value of 'in' will be routed to O1.

To achieve this, we can AND 'in' with '`sel', sending that output to O0. We also AND 'in' with 'sel', sending that output to O1.

Mux

A Multiplexer (MUX) is basically a selector. It has two input pins and a selector pin. Based on the selector, it selects one of the input pins.

If the selector is 0, then 'a' is selected, and if selector is 1, then 'b' is selected.

Let's start with an Axiom. Anything ANDed with 1 will result in that thing. So, 'a' AND 1 = 'a'

If we AND 'a' with NOT(selector), then the output of that AND gate (let's call it a1) will be 'a' if selector is 0. Similarly, if we AND 'b' with the selector, then the output of that AND gate (let's call it a1) will be 'b' if the selector is 1.

But along with this, we actually have to implement a conditional. If selector is 0, then 'a', else 'b'. The way to implement conditionals with logic gates is using the OR gate.

Now, if selector is 0, then 'a1' will carry the value of 'a', and 'a2' will carry 0. If selector is 1, then 'a1' will carry 0, and 'a2' will carry, the value of 'b'. Thus if we perform a1 OR a2, then we will get the correct answer.

Xor chip

Built an Xor chip

Or Chip

I have built the Or chip.

And Chip

Completed the And chip

Remember:

If there is a bug in the hdl program, such as incorrectly naming a part, it will simply not load the chip, but will not throw any errors.

Not chip

Completed the Not chip

Some basic notes for chapter 1

I have started reading chapter 1, and am having an absolutely awesome time re-learning so many of these things. Honestly, I had no clue how much I had forgotten.

In this blog post, I am going to enter a few notes, and document my my process of understanding various concepts I come across in this chapter.

Fact 1:

The simplest way to specify a boolean function is to enumerate all the possible values of the function's input variables along with the function's output for each set of input. This is also known as the truth table.

Fact 2:

Every boolean function can be represented with what is known as a Canonical representation. The truth table below represents a function with 3 variables.

x	y	z	f(x,y,z)
0	0	0	0
0	0	1	0
0	1	0	1
0	1	1	0
1	0	0	1
1	0	1	0
1	1	0	1
1	1	1	0

To get the canonical function, we have to OR all the rows which have 1 as the result. From the table above the canonical function will be:

f(x,y,z) = ^xy^z + x^y^z + xy^z

This shows, that all functions can be represented with a combination of AND, OR, and NOT

Fact 3 (with some sense making):

The book states in the last paragraph of page 9 - "the number of boolean functions that can be defined with n binary variables is 2^2^n". I had a hard time understanding this at first. But them I realized that n variables will lead to 2^n combinations (rows), and if we assume each row as a variable, then it is possible to have 2^2^n truth tables. Since each truth table is a function, we can say that for n variables, we can have 2^2^n functions.

Fact 4:

The NAND and NOR functions have an interesting theoretical property. Each of the functions AND, OR, and NOT, can be constructed using either NAND or NOR functions. And since any function can be represented using AND, OR, NOT (see fact 2), we can represent any function using only NAND, or NOR function.

Download and install the TECS hardware simulator

I downloaded the TECS software and unzipped it in ~/bin/tecs

Next, I ran HWSimulator.sh to check if the Hardware Simulator is working. It ran just fine, so I loaded the NAND chip ($TECS_HOME/builtInChips/NAND.HDL), and that too loaded fine.